Slow Speed Digital Design
Digital designers with experience in high-speed design sometimes forget that not every design is high-speed. Designing this way can lead to overengineered products.
When few months ago I watched a Robert Feranec video with the name Useful TIP: What Track Width To Use When Routing PCB?, I decided that I had to write something because I see there is a common tendency to apply high speed rules to designs that need not.
When a design is high speed?
When the time it takes a transition of logic state is similar or faster than the time it takes the signal to propagate from the origin to its destination.
Thus, it depends on the trace length and the speed of the logic. It does not depend on the data rate (although a high data rate requires fast logic, the reverse is not true).
What happens when a circuit is a high speed one?
In this case, Ohm’s law does not directly apply. The source does not ‘see’ the load; it ‘sees’ the line, which should be modeled as a transmission line. Unlike a lumped model, a transmission line has an RLC distributed model. See this link to go deeper on that.
A transmission line is characterized by its characteristic impedance (Z0). The designer that has to deal with signal integrity and the most common way of doing this is by matching impedance between the line and the source and/or the load. If you want to go deeper in that, you may want to have a look to this link.
One of the most annoying aspects of a high speed circuit is that the signal waveform differs in various parts of the circuit. It is not the same at the source, in different parts of the line, or at the load.
What does it happen when a circuits is not high speed?
Every high speed designer knows that using a lumped model does not drive correct results. But the opposite is not true. We could use transmission line considerations for low speed designs if we know what we are doing:
Most of the time, we can consider ideal traces. When not, the simplest model is a lumped one with series RL and parallel C. We can use transmission line calculators to calculate the stray inductance (L) and capacitance (C) of the line, which provide values of inductance and capacitance per unit length.
The source will immediately see the load, and Ohm’s law will apply regardless of the line’s characteristic impedance (that makes no sense in a lumped model). In other words, Z0 does not affect signal integrity.
Note that if you use approximations to calculate the line’s characteristic impedance, the approximations may lead to significant errors in many practical conditions. The calculators have their validity range.
Matching the impedance of the lines may lead to an overengineered design in which the traces may be forced to be too wide or too narrow. This may complicate the PCB design and/or increasing the cost of PCB manufacturing.
Matching lengths tend to be completely unnecessary. If you do the math, you will understand why. Remember this rule of thumb: signal propagation delay in microstrip over FR4 is double the delay of light in vacuum: about 6 ns/m, 6 ps/mm.
Regarding differential pairs, while it is adequate to keep the area of the signal loop as low as possible to avoid EMI problems, it makes no sense to apply restrictions of width and distance to differential transmission lines.
Life itself is complicated enough. Don’t make it more complicated than it is!